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Guest StefMeister

Verilog

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Guest StefMeister

Ma poate ajuta cineva cu modulul de test pentru exemplul din poza atasata? nu stiu exact cum as putea simula toate cele 3 module in acelasi modul de test..

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Păi add şi mult sînt deja instanţiate în pipelined_inner_prod, deci testbench-ul trebuie făcut doar pentru top. Deci scrie modulul de test pur şi simplu pentru pipelined_inner_prod.

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