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ABEL Hdl proiect


Guest Gheorghe Poalelungi

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Acesta este un cod VHDL (care l-am gasit pe net) modificat pentru conversie numar binar pe 5bit in BCD. Atentie nu este ABEL, cine vrea si poate sa il converteasca.

library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all; entity binary_bcd is    generic(N: positive := 5);    port(        clk, reset: in std_logic;        binary_in: in std_logic_vector(N-1 downto 0);        bcd0: out std_logic_vector(3 downto 0)        bcd1: out std_logic_vector(1 downto 0)    );end binary_bcd ; architecture behaviour of binary_bcd is    type states is (start, shift, done);    signal state, state_next: states;     signal binary, binary_next: std_logic_vector(N-1 downto 0);    signal bcds, bcds_reg, bcds_next: std_logic_vector(8 downto 0);    -- output register keep output constant during conversion    signal bcds_out_reg, bcds_out_reg_next: std_logic_vector(8 downto 0);    -- need to keep track of shifts    signal shift_counter, shift_counter_next: natural range 0 to N;begin     process(clk, reset)    begin        if reset = '1' then            binary <= (others => '0');            bcds <= (others => '0');            state <= start;            bcds_out_reg <= (others => '0');            shift_counter <= 0;        elsif falling_edge(clk) then            binary <= binary_next;            bcds <= bcds_next;            state <= state_next;            bcds_out_reg <= bcds_out_reg_next;            shift_counter <= shift_counter_next;        end if;    end process;     convert:    process(state, binary, binary_in, bcds, bcds_reg, shift_counter)    begin        state_next <= state;        bcds_next <= bcds;        binary_next <= binary;        shift_counter_next <= shift_counter;         case state is            when start =>                state_next <= shift;                binary_next <= binary_in;                bcds_next <= (others => '0');                shift_counter_next <= 0;            when shift =>                if shift_counter = N then                    state_next <= done;                else                    binary_next <= binary(N-2 downto 0) & '0';                    bcds_next <= bcds_reg(N-1 downto 0) & binary(N-1);                    shift_counter_next <= shift_counter + 1;                end if;            when done =>                state_next <= start;        end case;    end process;     bcds_reg(7 downto 4) <= bcds(7 downto 4) + 3 when bcds(7 downto 4) > 4 else                            bcds(7 downto 4);    bcds_reg(3 downto 0) <= bcds(3 downto 0) + 3 when bcds(3 downto 0) > 4 else                            bcds(3 downto 0);     bcds_out_reg_next <= bcds when state = done else                         bcds_out_reg;     bcd1 <= bcds_out_reg(5 downto 4);    bcd0 <= bcds_out_reg(3 downto 0); end behaviour;

si varianta de pe Wikipedia, adaptata pentru conversia unui numar pe 5biti (valori 31 .. 0):

library IEEE;use IEEE.STD_LOGIC_1164.ALL;use IEEE.numeric_std.all;entity bin2bcd_5bit is    Port ( nr_binar : in  STD_LOGIC_VECTOR (4 downto 0);           unitati : out  STD_LOGIC_VECTOR (3 downto 0);           zeci : out  STD_LOGIC_VECTOR (1 downto 0);          );end bin2bcd_5bit;architecture Behavioral of bin2bcd_5bit isbeginCONVERT: process(nr_binar)  -- variabila temporara  variable temp : STD_LOGIC_VECTOR (4 downto 0);    -- variabila care sa stocheze numarul in format BCD  -- organizat cum urmeaza  -- zeci = bcd(5 downto 4)  -- units = bcd(3 downto 0)  variable bcd : UNSIGNED (8 downto 0) := (others => '0');    begin    -- initializarea variabilei bcd    bcd := (others => '0');        -- copiem valoarea numarului binar in variabila temp    temp(4 downto 0) := nr_binar;        -- trecem prin bucla de 5 ori pentru ca avem 5 biti in numarul de convertit    for i in 0 to 4 loop          if bcd(3 downto 0) > 4 then         bcd(3 downto 0) := bcd(3 downto 0) + 3;      end if;            if bcd(7 downto 4) > 4 then         bcd(7 downto 4) := bcd(7 downto 4) + 3;      end if;          -- shiftam la stanga bcd cu 1 bit, copiem (adaugam) MSB al variabilei temp in LSB al variabilei bcd      bcd := bcd(7 downto 0) & temp(4);          -- shiftam temp la stanga cu 1 bit      temp := temp(3 downto 0) & '0';        end loop;     -- setam iesirile    unitati <= STD_LOGIC_VECTOR(bcd(3 downto 0));    zeci <= STD_LOGIC_VECTOR(bcd(5 downto 4));    end process CONVERT;              end Behavioral;
Edited by mars01
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Guest Gheorghe Poalelungi

Buna ziua la toti. Motivul acestei cereri de ajutor a fost din lipsa mea de timp. Sunt la master si muncesc si nu mai am timp pentru facultate, insa temele trebuiesc predate ca altfel in examen nu intru.Mai am si alte proiecte la alte obiecte care tot ma dau peste cap.Si va gresiti in privinta ca nu invat sau ca nu vreu, ba invat foarte bine si nu sunt de tipul ,,sa scot cu 5 min inainte de examen la imprimanta".Doar ca partea de microelectronica nu pre am inteles-o si nu mi se da usor, deoarece am facut la licenta electronica aplicata, si doar am cerut un ajutor cine poate si vrea,cel putin am incercat.Multumesc celor care mi-au dat idei si m-au ajutat, si nu judeca-ti oamenii dupa o simpla postare. O zi frumoasa tututor!

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Din cate imi dau seama, s-ar parea ca ce am postat eu este tangential la ce ai tu nevoie.

Ai aici o aplicatie care iti face diagramele Karnaugh: http://k-map.sourceforge.net/

 

Avand in vedere ca problema se poate rezolva intr-un mod concurent pasii care trebuie urmati sunt urmatorii:

 

1. Realizare diagrama Karnaugh cu 5 variabile

2. Obtinerea ecuatiilor pentru fiecare bit al codului BCD, adica mai exact 4+2 biti => 6 ecuatii care vor avea 5 variabile - softul de mai sus iti face acest lucru. Acestea se pot implementa cu porti SAU si SI.

3. Descrierea acestor ecuatii in limbajul ABEL HDL.

Edited by mars01
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si nu judeca-ti judecati oamenii dupa o simpla postare.

Ba asta e singurul lucru dupa care judecam - dupa continutul posturilor.

Vrei sa fii judecat cum crezi ca ti se cuvine, fa un efort si posteaza corespunzator.

In rest, scuzele mi se par macar puerile.

Da' ai dreptate, mai bine evit sa postez aici.

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Guest Gheorghe Poalelungi

L-am facut. Pentru cine doresc :

 

MODULE CONVERTOR
TITLE 'Convertor binar - BCD'
@alternate
declarations
A, B, C, D, E pin 2, 3, 4, 5, 6;
f, g, h, i, j, k pin 15, 16, 17, 18, 19, 20 istype 'com';
equations
f = A&B&/C+A&C;
g = /A&B&/C&D+/A&B&C&/D+A&/B&/C+B&C&D;
h = /A&B&/C&/D+A&/B&/C&D+A&B&C&/D;
i = /A&/B&C&/D+/A&C&D+A&/C&/D+A&B&/C&D;
j = /A&/B&/C&D+/A&B&C&/D+A&/B&/C&/D+/B&C&D+A&B&/C&D;
k = E;
test_vectors
([A, B, C, D, E] ->[f, g, h, i, j, k])
[0, 0, 0, 0, 0] ->[0, 0, 0, 0, 0, 0];
[0, 0, 0, 0, 1] ->[0, 0, 0, 0, 0, 1];
[0, 0, 0, 1, 0] ->[0, 0, 0, 0, 1, 0];
[0, 0, 0, 1, 1] ->[0, 0, 0, 0, 1, 1];
[0, 0, 1, 0, 0] ->[0, 0, 0, 1, 0, 0];
[0, 0, 1, 0, 1] ->[0, 0, 0, 1, 0, 1];
[0, 0, 1, 1, 0] ->[0, 0, 0, 1, 1, 0];
[0, 0, 1, 1, 1] ->[0, 0, 0, 1, 1, 1];
[0, 1, 0, 0, 0] ->[0, 0, 1, 0, 0, 0];
[0, 1, 0, 0, 1] ->[0, 0, 1, 0, 0, 1];
[0, 1, 0, 1, 0] ->[0, 1, 0, 0, 0, 0];
[0, 1, 0, 1, 1] ->[0, 1, 0, 0, 0, 1];
[0, 1, 1, 0, 0] ->[0, 1, 0, 0, 1, 0];
[0, 1, 1, 0, 1] ->[0, 1, 0, 0, 1, 1];
[0, 1, 1, 1, 0] ->[0, 1, 0, 1, 0, 0];
[0, 1, 1, 1, 1] ->[0, 1, 0, 1, 0, 1];
[1, 0, 0, 0, 0] ->[0, 1, 0, 1, 1, 0];
[1, 0, 0, 0, 1] ->[0, 1, 0, 1, 1, 1];
[1, 0, 0, 1, 0] ->[0, 1, 1, 0, 0, 0];
[1, 0, 0, 1, 1] ->[0, 1, 1, 0, 0, 1];
[1, 0, 1, 0, 0] ->[1, 0, 0, 0, 0, 0];
[1, 0, 1, 0, 1] ->[1, 0, 0, 0, 0, 1];
[1, 0, 1, 1, 0] ->[1, 0, 0, 0, 1, 0];
[1, 0, 1, 1, 1] ->[1, 0, 0, 0, 1, 1];
[1, 1, 0, 0, 0] ->[1, 0, 0, 1, 0, 0];
[1, 1, 0, 0, 1] ->[1, 0, 0, 1, 0, 1];
[1, 1, 0, 1, 0] ->[1, 0, 0, 1, 1, 0];
[1, 1, 0, 1, 1] ->[1, 0, 0, 1, 1, 1];
[1, 1, 1, 0, 0] ->[1, 0, 1, 0, 0, 0];
[1, 1, 1, 0, 1] ->[1, 0, 1, 0, 0, 1];
[1, 1, 1, 1, 0] ->[1, 1, 0, 0, 0, 0];
[1, 1, 1, 1, 1] ->[1, 1, 0, 0, 0, 1];
END
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