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mars01

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  1. Proiectul MPLABX v6.15 + XC8 v2.41 (free) Contine fisierul .HEX Ceas_GPS.zip
  2. Eu zic sa incerci cu ultima versiune de MPLab X. Se referea la altceva, ce am discutat pe MP.
  3. Linia aceasta este gresita, am copiat gresit dintr-un alt program: ANSELAbits.ANSA0 = 1; // Disable digital input on RA0 Corect este asa: ANSELbits.ANS0 = 1; // Disable digital input on RA0 BTW, daca nu ai realizat, se compileaza cu compilatorul XC8 al Microchip.
  4. Bună, încearcă asta: // Configuration bits // CONFIG1H #pragma config FOSC = IRC // Oscillator Selection bits (Internal RC oscillator) #pragma config PLLEN = OFF // 4 X PLL Enable bit (PLL is under software control) #pragma config PCLKEN = ON // Primary Clock Enable bit (Primary clock enabled) #pragma config FCMEN = OFF // Fail-Safe Clock Monitor Enable (Fail-Safe Clock Monitor disabled) #pragma config IESO = OFF // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled) // CONFIG2L #pragma config PWRTEN = OFF // Power-up Timer Enable bit (PWRT disabled) #pragma config BOREN = SBORDIS // Brown-out Reset Enable bits (Brown-out Reset enabled in hardware only (SBOREN is disabled)) #pragma config BORV = 19 // Brown Out Reset Voltage bits (VBOR set to 1.9 V nominal) // CONFIG2H #pragma config WDTEN = OFF // Watchdog Timer Enable bit (WDT is controlled by SWDTEN bit of the WDTCON register) #pragma config WDTPS = 32768 // Watchdog Timer Postscale Select bits (1:32768) // CONFIG3H #pragma config HFOFST = ON // HFINTOSC Fast Start-up bit (HFINTOSC starts clocking the CPU without waiting for the oscillator to stablize.) #pragma config MCLRE = OFF // MCLR Pin Enable bit (RA3 input pin enabled; MCLR disabled) // CONFIG4L #pragma config STVREN = ON // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset) #pragma config LVP = OFF // Single-Supply ICSP Enable bit (Single-Supply ICSP disabled) #pragma config BBSIZ = OFF // Boot Block Size Select bit (1kW boot block size) #pragma config XINST = OFF // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode)) // CONFIG5L #pragma config CP0 = OFF // Code Protection bit (Block 0 not code-protected) #pragma config CP1 = OFF // Code Protection bit (Block 1 not code-protected) // CONFIG5H #pragma config CPB = OFF // Boot Block Code Protection bit (Boot block not code-protected) #pragma config CPD = OFF // Data EEPROM Code Protection bit (Data EEPROM not code-protected) // CONFIG6L #pragma config WRT0 = OFF // Write Protection bit (Block 0 not write-protected) #pragma config WRT1 = OFF // Write Protection bit (Block 1 not write-protected) // CONFIG6H #pragma config WRTC = OFF // Configuration Register Write Protection bit (Configuration registers not write-protected) #pragma config WRTB = OFF // Boot Block Write Protection bit (Boot block not write-protected) #pragma config WRTD = OFF // Data EEPROM Write Protection bit (Data EEPROM not write-protected) // CONFIG7L #pragma config EBTR0 = OFF // Table Read Protection bit (Block 0 not protected from table reads executed in other blocks) #pragma config EBTR1 = OFF // Table Read Protection bit (Block 1 not protected from table reads executed in other blocks) // CONFIG7H #pragma config EBTRB = OFF // Boot Block Table Read Protection bit (Boot block not protected from table reads executed in other blocks) // #pragma config statements should precede project file includes. // Use project enums instead of #define for ON and OFF. #include <xc.h> #define _XTAL_FREQ 4000000 // Internal oscillator frequency (4MHz) void main() { // Disable comparators CM1CON0bits.C1ON = 0; CM2CON0bits.C2ON = 0; // Configure oscillator settings OSCCONbits.IRCF = 0b101; // Set internal oscillator to 4MHz OSCCONbits.SCS = 0b00; // Internal oscillator used for system clock // Initialize DAC using VREF TRISAbits.TRISA0 = 0; // Set RA0 as output ANSELAbits.ANSA0 = 1; // Disable digital input on RA0 TRISB = 0x00; // Set all PORTB pins as outputs // Configure voltage reference for DAC VREFCON1bits.D1EN = 1; // Enable DAC VREFCON1bits.D1LPS = 1; // Select positive reference source disabled in Low Power mode VREFCON1bits.DAC1OE = 1; // Enable DAC output on DAC1OUT (CVREF) pin VREFCON1bits.D1PSS = 0b00; // Select VDD as positive source VREFCON1bits.D1NSS = 0; // Select VSS as negative source // Main loop while (1) { // Increase DAC output from 0 to 31; 5bit DAC max value is 32 for (unsigned int value = 0; value <= 31; value++) { VREFCON2bits.DAC1R = value; // Set DAC output value __delay_us(100); // Delay for smooth transition (adjust as needed) } // Decrease DAC output from 31 to 0 for (unsigned int value = 31; value >= 0; value--) { VREFCON2bits.DAC1R = value; // Set DAC output value __delay_us(100); // Delay for smooth transition (adjust as needed) } } }
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